1. Field of the Invention
The present invention relates to the field of automated test equipment (ATE). In particular, the present invention relates to a technique of loading of a test plan in the ATE for semiconductor testing.
2. Description of the Related Art
The most part of cost in manufacturing semiconductor is for development and maintenance of a test program for testing an integrated circuit for practicability and functionality. Many hours of operations on actual tester hardware have been needed for the purpose of performing the development and maintenance. That is, a conventional semiconductor tester has little or no capability to simulate a test program. Under such restriction, an engineer is forced to debug his/her test program in the actual tester hardware.
Recently, an emulator for test equipment has been provided. Accordingly, functionality of a test program can be verified without requiring the use of any high-priced test equipment. For example, U.S. Patent Application Publication No. US 2005/0039079 A1, assigned to the assignee of the present invention, discloses an emulator for simulating a module type test system by using a test program, a vender module and a corresponding device-under-test (DUT).
Recently, many functions have been integrated into one chip, significantly advancing the speed, size and function of a device. That causes a big problem that testing of the device needs to catch up with such trends of advancement and complication in functionality and also needs to improve capability of analyzing a device to shorten a turn around time (TAT).
Conventional test plan program is monolithic, which means that a single test plan program is defined for a device. Accordingly, as more and more functions are incorporated into such devices, the size of the test plan program is increasing. That not only adds to a load of development of the test plan program but also increase a time required to load the test plan program to test equipment. Particularly, in an actual occasion of operating test equipment, the entire of the monolithic test plan of a current model needs to be deleted (unloaded) from the test equipment and the entire of a new test plan needs to be reloaded to the test equipment each time a DUT is changed to another DUT with a different model. When various models of devices are manufactured by a small number for each model or if different models of devices need to be tested in a day, time will be consumed just for loading the test plan program.
Recent semiconductor devices are typically configured with a great number of blocks combined. When a DUT to be tested by the test equipment is changed to another DUT with a different model, the first DUT and the second DUT may have most of the great number of blocks in common with only some blocks being different from each other. If the test equipment is adapted to require only the test programs, pattern files and the like relating to the different blocks to be loaded and unloaded effectively, the time for loading can be shorter, which leads to a shorter TAT.
The present invention is adapted in view of such circumstances. Several aspects according to the present invention is to modularize a test plan for test equipment by dividing the test plan into a plurality of sub-test plans, exchange (unload and reload) only different test plans by detecting a difference between the test plans before and after the changing of the DUTs when the DUTs with different models are changed, and exchange (unload and reload) different pattern programs which differ before and after the changing of the DUTs by managing the pattern programs which are used for the sub-test plans.